1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory. In particular, the present invention relates to a charge trapping memory of a split gate type and a manufacturing method thereof.
2. Description of Related Art
A flash memory and a charge trapping memory are known as a electrically erasable and programmable nonvolatile semiconductor memory. The charge trapping memory stores data by using an element that is capable of trapping charges. The element for trapping charges is a MONOS (Metal Oxide Nitride Oxide Silicon) transistor, for example. The MONOS transistor is a type of MIS (Metal Insulator Silicon) transistor, where an ONO (Oxide Nitride Oxide) film obtained by laminating a silicon oxide film, a silicon nitride film and a silicon oxide film in this order is used as a gate insulating film thereof.
The silicon nitride film in the ONO film has property trapping charges. For example, it is possible to inject electrons into the silicon nitride film by applying appropriate potentials to a gate electrode, source/drain and a substrate. In a case where electrons are trapped by the silicon nitride film, a threshold voltage of the MONOS transistor is increased as compared with a case where electrons are not trapped. On the contrary, when the trapped electrons are drawn out from the silicon nitride film, the threshold voltage is decreased. By utilizing such change in the threshold voltage, the MONOS transistor can nonvolatilely store data “1” and “0”. That is, the charge trapping memory stores data by utilizing the MONOS transistor as a memory cell transistor.
Japanese Patent Publication JP-2005-228957A and Japanese Patent Publication JP-2006-253433A disclose a charge trapping memory of a split gate type where one memory cell has two gate electrodes. More specifically, one memory cell is provided with a first gate electrode and a second gate electrode that are arranged side by side on a channel region. An ONO film is formed between the first gate electrode and the channel region, and an ordinary gate insulating film is formed between the second gate electrode and the channel region. According to this related technique, the two gate electrodes both are formed by etching-back technique.